Efficient Multiplexer Synthesis

The multiplexer is a common standard sub-circuit used frequently in the datapath logic of complex designs, typically to provide a path for routing operands to operations and operation results to destination registers. During RTL synthesis, multiplexers are used for realizing ifthen-else and case statements in the RTL design description. In this paper, we describe a new heuristic algorithm for synthesizing efficient multiplexers consisting of a tree of multiplexer components from a library. Area minimization is our primary goal. Hence, we first generate an area-minimal implementation of a multiplexer, using multiplexer components from the library. Subsequently, we minimize the delay of the area-minimal implementation. We have implemented the algorithm in a high-level synthesis tool. Experimental results show that our algorithm almost always generates the minimum-area multiplexer, and consistently generates smaller multiplexers than commercial tools that synthesize multiplexers. Moreover, experimental results show that the multiplexers generated by our technique are efficient in terms of propagation delay when compared to commercial tools.